Title :
VLSI Gate array prime radix Fourier transform processor
Author :
Spreadbury, D.J. ; Roberts, T. M Rees
Author_Institution :
GEC Avionics, Hertfordshire, England
Abstract :
This paper describes the development of the transform algorithm which results in the design of two gate array circuits for implementing a high performance Prime Radix Discrete Fourier Transform (PRAT) function, that will form a key processing primitive for the new Control Ordered Sonar Hardware (COSH) signal processing architecture, currently under development at the Admiralty Research Establishment (A.R.E. Portland, England) [1]. Consideration is given to the structure and derivation of a high performance DFT algorithm whose kernel is a parallel canonic realisation using Curtis-Goertzel second order recursive filters. The way in which the resulting circuit topology maps onto gate array implementation is then presented.
Keywords :
Algorithm design and analysis; Array signal processing; Circuits; Discrete Fourier transforms; Fourier transforms; Hardware; Signal design; Signal processing algorithms; Sonar; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
DOI :
10.1109/ICASSP.1985.1168166