A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks

Author

Vanderbauwhede, W. ; Chalamalasetti, S.R. ; Purohit, S. ; Margala, M.

Author_Institution

Sch. of Comput. Sci., Univ. of Glasgow, Glasgow, UK

fYear

2011

fDate

4-8 July 2011

Firstpage

461

Lastpage

467

Abstract

MORA-C++ is a novel, high-efficiency FPGA dataflow programming framework. The framework, which consists of a compile-time configurable network of Vectorized Processors-in-Memory (PIM) cores, is programmed using a high-level C++ API. In this paper we present our work on support for vectorized cores and variable-size data path widths. Measurement results on our implementation for the SGI RC-100 platform show that, by instantiating over a thousand customized cores, the MORA-C++ framework can achieve throughputs very close to the I/O bandwidth of the system for a high-performance DCT application.

Keywords

C++ language; application program interfaces; data flow computing; field programmable gate arrays; vector processor systems; FPGA dataflow programming; I-O bandwidth; MORA-C++; SGI RC-100 platform; compile-time configurable network; high-level C++ API; high-performance DCT application; lines of code; vector processor network; vectorized processors-in-memory core; Benchmark testing; Discrete cosine transforms; Discrete wavelet transforms; Field programmable gate arrays; Programming; Random access memory; Throughput; High-level FPGA Programming; Multimedia Processing; Reconfigurable Processor; Vector Processor Network;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing and Simulation (HPCS), 2011 International Conference on

Conference_Location

Istanbul

Print_ISBN

978-1-61284-380-3

Type

conf

DOI

10.1109/HPCSim.2011.5999875

Filename

5999875