Title :
Source-Coupled Logic (SCL): Operation and Delay Analysis
Author :
Azaga, Mohamed ; Othman, Masuri
Author_Institution :
VLSI Design Center, Bangi
fDate :
Oct. 29 2006-Dec. 1 2006
Abstract :
This work describe and present the analysis for the source-coupled logic (SCL) inverter. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics, and the effect of noise margin. Finally, the inverter gate delay model is described, and the effect of biasing current on the delay is shown. All simulation is done based on the 0.18 mu Silterra process, and using Cadence Spectre simulation platform. The result shows that, the delay of the SCL inverter is decreased as biasing current increase.
Keywords :
logic circuits; logic gates; Cadence Spectre simulation platform; Silterra process; inverter gate delay model; source-coupled logic inverter; Circuit simulation; Delay effects; Logic circuits; Logic design; Logic gates; MOS devices; Pulse inverters; Rails; Very large scale integration; Voltage;
Conference_Titel :
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-9730-4
Electronic_ISBN :
0-7803-9731-2
DOI :
10.1109/SMELEC.2006.381088
