Source-Coupled Logic (SCL): Operation and Delay Analysis

This work describe and present the analysis for the source-coupled logic (SCL) inverter. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics, and the effect of noise margin. Finally, the inverter gate delay model is described, and the effect of biasing current on the delay is shown. All simulation is done based on the 0.18 mu Silterra process, and using Cadence Spectre simulation platform. The result shows that, the delay of the SCL inverter is decreased as biasing current increase.