Constraint-based channel routing for analog and mixed analog/digital circuits

A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges and increasing the weights of edges in the VC graph, in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments, while attempting to cause minimum increase in the channel height due to the constraints. A technique to match the parasitics for symmetrical pairs of nets in the channel is also proposed.<>