A cepstrum chip: architecture and implementation

The cepstrum coefficients have been widely used for speech signal representation and play a very important role in recognition accuracies. We present a low cost architecture for VLSI implementation of LPC-based cepstrum algorithm. The circuit performs the cepstrum operation for each frame of the speech data. A pipelining architecture leads to high speed performance up to speech recognition rate. The cepstrum chip is fabricated in 1.2 μm double-metal CMOS technology after the physical design and circuit verification. On the whole, the chip can process 18.3 MHz sampled data and it contains about 24000 transistors which occupy 227.5×213.3 mils² area. It has been shown to be fully functional and is the first working cepstrum chip