Title :
A parallel algorithm for hierarchical circuit extraction
Author :
Belkhale, K.P. ; Banerjee, P.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
An algorithm is presented that combines the benefits of hierarchical analysis and parallelism. The input is a hierarchical description of the circuit. The authors formulate and solve a general problem in scheduling. The parallel algorithm for hierarchical circuit extraction has been implemented on an Encore shared memory multiprocessor.<>
Keywords :
VLSI; circuit layout CAD; parallel algorithms; scheduling; Encore shared memory multiprocessor; PITS algorithm; VLSI layout; hierarchical analysis; hierarchical circuit extraction; hierarchical description; parallel algorithm; parallelism; partitionable independent task scheduling; scheduling; Algorithm design and analysis; Circuits; Concurrent computing; Data mining; Distributed computing; Geometry; Parallel algorithms; Parallel processing; Parameter estimation; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129890
