Title :
Power dissipation in deep submicron CMOS digital circuits
Author :
Gu, R.X. ; Elmasry, M.I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
30 Apr-3 May 1995
Abstract :
In this paper, a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits is introduced. The model is based on Berkeley Short-Channel (BSIM) model and fits HSPICE simulation results well. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented
Keywords :
CMOS logic circuits; SPICE; VLSI; circuit CAD; circuit analysis computing; digital simulation; integrated circuit design; integrated circuit modelling; logic CAD; Berkeley short-channel model; HSPICE simulation results; analytical model; deep submicron CMOS digital circuits; design methodology; power-delay product; standby power dissipation; supply voltages; switching power dissipation; threshold voltages; Analytical models; CMOS digital integrated circuits; Circuit simulation; Design methodology; Digital circuits; Power dissipation; Semiconductor device modeling; Switching circuits; Threshold voltage; Upper bound;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521444
