DocumentCode
299158
Title
Floorplanning for low power designs
Author
Chao, Kai-Yuan ; Wong, D.F.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
1
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
45
Abstract
In this paper, a floorplanner for low power designs is presented. Our objective is to optimize total power consumption and area during the selection and placement of circuit modules. Furthermore, our method considers the reduction of power line noises, thermal reliability problems, and performance requirements
Keywords
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; integrated circuit noise; integrated circuit reliability; chip area optimisation; circuit modules; floorplanning; low power designs; performance requirements; power line noise reduction; thermal reliability problems; total power consumption optimisation; Circuit noise; Circuit synthesis; Clocks; Design optimization; Energy consumption; Frequency; Portable computers; Power dissipation; Signal design; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.521447
Filename
521447
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