CADICS-cyclic analog-to-digital converter synthesis

Author

Jusuf, Gani ; Gray, Paul R. ; Sangiovanni-Vincentelli, Alberto L.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1990

fDate

11-15 Nov. 1990

Firstpage

286

Lastpage

289

Abstract

CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit CAD; circuit layout CAD; CADICS; capacitor trim array; cyclic analog-to-digital converter synthesis; internal self-calibration; layouts; netlists; technology-independent synthesis tool; Analog circuits; Analog-digital conversion; Capacitors; Circuit synthesis; Design automation; Power dissipation; Sampling methods; Silicon; Switches; Switching converters;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-2055-2

Type

conf

DOI

10.1109/ICCAD.1990.129904

Filename

129904