Title :
On determining scan flip-flops in partial-scan designs
Author :
Lee, D.H. ; Reddy, S.M.
Author_Institution :
Iowa Univ., Iowa City, IA, USA
Abstract :
A report is presented on procedures investigated to determine flip-flops to be scanned in partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs. Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions.<>
Keywords :
circuit CAD; logic CAD; logic testing; sequential circuits; S-graphs; benchmark circuits; heuristic methods; minimal feedback vertex set; partial-scan designs; scan flip-flops; sequential circuits; Automatic testing; Benchmark testing; Circuit testing; Cities and towns; Feedback; Flip-flops; Hardware; Sequential analysis; Sequential circuits; Telephony;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129914
