A fast algorithm for performance-driven placement

An algorithm was developed for the placement of small-cell ICs subject to performance constraints that is efficient in terms of speed and memory usage. The approach models wirelength using a nonlinear cost function similar to that of R.S. Tsay et al. (1988) and a timing model which uses a block-oriented representation of paths like that of M.A.B. Jackson and E.S. Kuh (1989). The timing constraints are implicitly represented using a network and nonlinear programming techniques are used to solve the wirelength minimization problem while satisfying the constraints. This allows critical paths to dynamically adjust while the placement changes to minimize wirelength. The solution of the nonlinear programming problem yields an initial placement of cells that may violate slot constraints. The authors propose hierarchical solution techniques to resolve the slot constraints. By exploiting structure inherent in the formulation, a large reduction is achieved in the number of variables that represent the problem. Additionally, developing special techniques to take advantage of the interaction between the timing model and the physical position of the cells enabled the authors to achieve a speed-up of 10-15 times over Jackson and Kuh (1989) even with a crude implementation of the algorithm.<>