Title :
A 1.6 Gb/s CMOS phase-frequency locked loop for timing recovery
Author :
Soyuer, Mehmet ; Ainspan, Herschel A. ; Ewen, John F.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
30 Apr-3 May 1995
Abstract :
A fully monolithic phase-frequency locked loop (PFLL) for timing recovery applications is implemented in a 0.25 μm digital CMOS technology. The circuit uses a digital phase-frequency detector (PFD) which provides a wide frequency acquisition capability with NRZ data inputs. An on-chip charge-pump loop filter is used to minimize jitter. The total power consumption is 250 mW from 2.5 V at 1.6 Gb/s
Keywords :
CMOS digital integrated circuits; digital phase locked loops; jitter; timing; 0.25 micron; 1.6 Gbit/s; 2.5 V; 250 mW; NRZ data inputs; digital CMOS technology; digital phase-frequency detector; monolithic PFLL; onchip charge-pump loop filter; phase-frequency locked loop; timing recovery; wide frequency acquisition capability; CMOS technology; Charge pumps; Circuits; Energy consumption; Filters; Jitter; Optical signal processing; Phase detection; Phase frequency detector; Timing;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521482
