DocumentCode :
299188
Title :
Minimum-cost bounded-skew clock routing
Author :
Cong, Jason ; Koh, Cheng-Kok
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Volume :
1
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
215
Abstract :
In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm constructs a bounded-skew tree (BST) in two steps: (i) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ii) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of routing solutions with skew and wirelength trade-off
Keywords :
circuit layout CAD; circuit optimisation; clocks; network routing; network topology; trees (mathematics); BST/DME; binary tree; bottom-up phase; bounded-skew clock routing; bounded-skew tree; clock entry points; deferred-merge embedding; path-length skew bound; routing solutions; shortest-distance feasible regions; top-down phase; total wirelength; wirelength trade-off; Binary search trees; Binary trees; Clocks; Contracts; Costs; Delay; Routing; Scholarships; Synchronization; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.521489
Filename :
521489
Link To Document :
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