Title :
An IDDQ fault model to facilitate the design of built-in current sensor (BICSs)
Author :
Tang, Jing-Jou ; Liu, Bin-Da ; Lee, Kuen-Jong
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
30 Apr-3 May 1995
Abstract :
In-this paper, we present an efficient and accurate IDDQ fault modeling technique for digital CMOS circuit. Both the normal and faulty “current” behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is obtained. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given
Keywords :
CMOS digital integrated circuits; electric current measurement; electric sensing devices; fault diagnosis; integrated circuit design; integrated circuit modelling; integrated circuit testing; IDDQ fault model; built-in current sensor; circuit design; digital CMOS circuit; parasitic capacitive parameters; parasitic inductive parameters; Adders; Automatic testing; Boolean functions; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Logic design; Semiconductor device modeling; Steady-state;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521533
