Implementation of 1024-Point FFT Algorithm Based on FPGA

Author

Lihui, Pang ; Jingchang, Yang

Author_Institution

Inst. of Electr. & Inf., Xihua Univ., Chengdu, China

fYear

2010

fDate

25-27 June 2010

Firstpage

4695

Lastpage

4697

Abstract

This paper presents a program, the implementation of 1024-Point FFT algorithm based on FPGA. Considering from the operation speed and implementation complexity, this design adopts the algorithm of radix-2 and decimation in time. And cure the data of twiddle factor in the ROM block. This design uses the finite state machine control reading the data of twiddle factor, as well as coordinate each modules of FFT work in steady-state. In the end, the comparison of the results of the design with the operation results of Matlab is given, verified the correctness of the algorithm.

Keywords

digital arithmetic; fast Fourier transforms; field programmable gate arrays; finite state machines; 1024-Point FFT Algorithm; FPGA; Matlab; ROM block; finite state machine control; radix-2 algorithm; twiddle factor; Algorithm design and analysis; Digital signal processing; Discrete Fourier transforms; Field programmable gate arrays; Hardware design languages; Random access memory; Read only memory; decimation in time; finite state machine; radix-2; widdle factor;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Control Engineering (ICECE), 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-6880-5

Type

conf

DOI

10.1109/iCECE.2010.1136

Filename

5630496