Implementation of Speed Match Circuit Design between DSP and Peripheral Chips Using CPLD

Author

Song, Yongxian ; Zhang, Hanxia ; Ma, Juanli ; He, Naibao

Author_Institution

Inst. of Electron. Eng., Huaihai Inst. of Technol., Lianyungang, China

fYear

2010

fDate

25-27 June 2010

Firstpage

4698

Lastpage

4701

Abstract

In some industry instrument and automation equipment, the digital signal processor (DSP) usually needs establishing the interface with different speed peripheral chips. TMS320Cxx provide two kinds of mechanism to match with out side chips. One can insert 0~7 wait periods by setting inner control register. Another is to provide the READY signal pin, it can produce arbitrarily number of wait period with the exterior control circuit. In this paper, CPLD is employed to generate the waiting sign by the correlative hardware circuit diagram and VHDL language programs method respectively. The speed match circuits have been realized between DSP and peripheral chips. It can simplify the program and raise the whole performance speed of system.

Keywords

digital signal processing chips; hardware description languages; network synthesis; peripheral interfaces; CPLD; DSP chips; READY signal pin; VHDL language programs; automation equipment; correlative hardware circuit diagram; digital signal processor; exterior control circuit; inner control register; peripheral chips; speed match circuit design; speed peripheral chips; Clocks; Delay; Digital signal processing; Flip-flops; Programming; Random access memory; Software; CPLD; DSP; VHDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Control Engineering (ICECE), 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-6880-5

Type

conf

DOI

10.1109/iCECE.2010.1137

Filename

5630497