DocumentCode
299258
Title
A digit-serial VLSI architecture for delayed LMS adaptive FIR filtering
Author
Wang, Chin-Liang ; Chen, Ching-Chia ; Chang, Che-Fu
Author_Institution
Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
1
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
545
Abstract
In this paper, we present a digit-serial VLSI architecture for realization of an adaptive FIR filter equipped with the delayed least mean square (LMS) algorithm. The architecture is attractive for use in applications where bit-serial arithmetic is too slow and bit-parallel arithmetic requires too much hardware or cannot reach the desired convergence performance
Keywords
FIR filters; VLSI; adaptive filters; delays; digital arithmetic; digital filters; digital signal processing chips; least mean squares methods; adaptive FIR filtering; delayed LMS algorithm; delayed least mean square algorithm; digit-serial VLSI architecture; Adaptive filters; Arithmetic; Delay; Filtering; Finite impulse response filter; Least squares approximation; Logic; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.521571
Filename
521571
Link To Document