Author_Institution :
Dept. of Comput. Sci. & Technol., Guangdong Univ. of Foreign Studies, Guangzhou, China
Abstract :
In recent years, China gradually put more resources in the DDS study, but it is relatively far from the international level, especially in the aspect of DDS hardware design. So, according to the status mentioned above, it was described in detail about how to simulate and achieve a DDS based FPGA in this paper. Firstly, the frame of DDS based FPGA was constructed and the algorithm was analyzed, the module be plotted as well. And on this basis mentioned, the Verilog HDL language was used to execute RTL-level functional simulation and write testing platform, and then all the digital parts design and simulation and even the timing analysis as well as the synthesis optimization were completed. To meet the requirements of high-frequency and low jitter, the synthesis repeated several times and such factors as timing, area, power consumption were fully considered, the simulation result after layout was proved closed to the actual waveform. There are better results in the design of each functional module in the synthesis, as well as timing, area, power and other aspects, and it was proved to meet the engineering design requirements and have greater reusability and practicality.
Keywords :
direct digital synthesis; field programmable gate arrays; hardware description languages; optimisation; timing; China; DDS; FPGA; RTL-level functional simulation; Verilog HDL language; direct digital frequency synthesizer; optimization; timing; Clocks; Field programmable gate arrays; Frequency control; Frequency synthesizers; Hardware design languages; Presses; Read only memory; DDS; FPGA; synthesis and timing; verilog hdl;
