Improving digital MOS macromodel accuracy

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors have not been previously provided. Errors, if secondary effects are not addressed, may total 100% or more. The significant improvement in simulation accuracy using these proposed techniques is shown