A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

Author

Yamaoka, Hiroaki ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Graduate Sch. of Eng., Tokyo Univ., Japan

fYear

2001

fDate

2001

Firstpage

3

Lastpage

4

Abstract

In this paper, a high-speed PLA based on latch sense amplifiers and a charge sharing scheme is presented. The circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By latch sense amplifiers, a read-out scheme sensing the differential voltage of dual-rail bit-lines caused by charge sharing is used for high-speed operation. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-μm double-poly, triple-metal CMOS process. Results of HSPICE simulation are 2.9 times faster than the conventional CMOS circuit. The measured results show a good agreement with the simulation

Keywords

CMOS logic circuits; comparators (circuits); high-speed integrated circuits; programmable logic arrays; 0.6 micron; array logic circuits; binary comparator; charge sharing scheme; control blocks; differential voltage sensing; double-poly triple-metal CMOS process; dual-rail bit-lines; high-speed PLA; latch sense amplifiers; logic cell arrays; read-out scheme; Circuit simulation; Inverters; Latches; Logic arrays; Logic circuits; Programmable logic arrays; Rail to rail amplifiers; Sequential circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913260

Filename

913260