Title :
Single chip 3D rendering engine integrating embedded DRAM frame buffer and hierarchical octet tree (MOT) array processor with bandwidth amplification
Author :
Park, Yong-Ha ; Han, Seon-Ho ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Abstract :
A single chip rendering engine that consists of a DRAM frame buffer, an SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56 mm2 prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35 μm CMOS Embedded Memory Logic (EML) technology
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; array signal processing; buffer circuits; edge detection; multimedia systems; reduced instruction set computing; rendering (computer graphics); video signal processing; 0.35 micron; 32 bit; CMOS embedded memory logic technology; DRAM frame buffer; RISC core; SRAM serial access memory; array processor; bandwidth amplification; edge processor; embedded DRAM frame buffer; frame buffers; hierarchical octet tree; low power 3D-graphics; pixel processors; single chip 3D rendering engine; Bandwidth; Clocks; Engines; Graphics; Multimedia systems; Random access memory; Reduced instruction set computing; Rendering (computer graphics); Semiconductor device measurement; Testing;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913263
