DocumentCode :
2992856
Title :
Robust testing a subset of paths - untested paths in the circuit
Author :
Sharma, Manish ; Patel, Janak H.
Author_Institution :
Illinois Univ., Urbana, IL, USA
fYear :
2004
fDate :
25-29 April 2004
Firstpage :
31
Lastpage :
36
Abstract :
In this paper we analyze the coverage of distributed delay defects, on untested but functionally sensitizable paths, achieved by robustly testing a subset of paths in the circuit. This is measured by translating the information gained from robust testing into a set of linear constraints on edge delays and then using these to bound the circuit delay. Surprisingly, the results of our experiments on ISCAS benchmark circuits show that robust testing of a subset of paths in the circuit, may not cover distributed delay defects on the remaining paths very well at all.
Keywords :
circuit optimisation; delays; integrated circuit modelling; integrated circuit testing; logic testing; benchmark circuits; circuit delay; circuit optimisation; distributed delay defects coverage; edge delays; linear constraints; robust testing; sensitizable paths; untested circuit path; Benchmark testing; Circuit faults; Circuit testing; Delay effects; Gain measurement; Robustness; Timing; Upper bound; Virtual manufacturing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2134-7
Type :
conf
DOI :
10.1109/VTEST.2004.1299222
Filename :
1299222
Link To Document :
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