Title :
Error correction algorithm for folding/interpolation ADC
Author :
Kobayashi, Haruo ; Sakayori, Hiroshi ; Tobari, Tsutomu ; Matsuura, Hiroyuki
Author_Institution :
Teratec Corp., Tokyo, Japan
fDate :
30 Apr-3 May 1995
Abstract :
This paper discusses digital error correction algorithms for folding/interpolation AD converters which yield to very simple circuitry. The relationships between error correction and input signal frequency have been clarified theoretically and also confirmed by simulation
Keywords :
analogue-digital conversion; error correction codes; interpolation; circuitry; digital error correction algorithm; folding/interpolation ADC; signal frequency; simulation; Analog-digital conversion; Capacitance; Circuit simulation; Clocks; Delay; Error correction; Frequency; Hardware; Interpolation; Reflective binary codes;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521613
