A novel memory architecture to achieve minimal rounding/truncation errors for N dimensional image transformation

This paper describes a novel memory architecture to minimize truncation error for implementing N-Dimension decomposable transformation using consecutive one dimension (1D) transformation approach. The memory architecture utilizes the effective bit representation not only achieving minimal truncation error with a constrained memory size, but also minimizing memory size to fulfill a given accuracy requirement. A 8×8 2-D IDCT macro that used the proposed architecture is implemented. The cell count for the macro is 43 K cells and occupies 6 mm² using 0.5 μm CMOS VLSI technology