High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

This paper presents the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using radix-4 modified Booth algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation to eta/2 and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efficiently using VHDL codes for 16 times16-bit signed numbers and successfully simulated and synthesized using ModelSim XE II 5.8c and Xilinx ISE 6.1i. As a proof of concept, the system is implemented on Xilinx Virtex-II Pro FPGA board.