A neural network implementation of an input access scheme in a high-speed packet switch

A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each output; thus, in an (n×n) switch there will be n² input queues. Using synchronous operation, at most one packet per input and output will be transferred at every slot. A neural network maximizing the throughput of this switch is determined, and the form of the energy function, its optimized parameters, and the connection matrix are given. Simulations with random inputs have yielded results close to optimal throughput. This neural network can be implemented with the existing technology for medium switching sizes