Title :
Yield analysis of logic circuits
Author :
Appello, D. ; Fudoli, A. ; Giarda, K. ; Gizdarski, E. ; Mathew, B. ; Tancorre, V.
Author_Institution :
TPA Mixed Signal Test Solution Group, ST Microelectron., Cornaredo, Italy
Abstract :
Complex SOC´s developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.
Keywords :
automatic test equipment; automatic test pattern generation; fault diagnosis; logic circuits; logic testing; system-on-chip; ATE data collection; ATPG diagnosis; SOC; failure analysis; logic circuits diagnosis; manufacturing test floor; test vectors generation; yield losses analysis; Automatic test pattern generation; Circuit analysis; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Instruments; Logic circuits; Manufacturing; Production;
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
Print_ISBN :
0-7695-2134-7
DOI :
10.1109/VTEST.2004.1299232
