DocumentCode
2993191
Title
Effects of bit line coupling on the faulty behavior of DRAMs
Author
Al-Ars, Zaid ; Hamdioui, Said ; van de Goor, Ad.J.
Author_Institution
Lab. of Comput. Eng., Delft Univ. of Technol., Netherlands
fYear
2004
fDate
25-29 April 2004
Firstpage
117
Lastpage
122
Abstract
With the shrinking dimensions of manufactured structures on memory chips and the increase in memory size, bit line coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of bit line coupling on the faulty behavior of DRAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a SPICE simulation model. Two bit line coupling mechanisms are identified, pre-sense and post-sense coupling, and found to have a partly opposing effect on the faulty behavior. In addition, the impact of neighboring cells on these coupling mechanisms is investigated.
Keywords
DRAM chips; SPICE; fault simulation; DRAM; SPICE simulation model; dynamic random access memory; post-sense coupling effects; pre-sense coupling effects; simulation based fault analysis; simulation program with integrated circuit emphasis; two bit line coupling mechanisms; Analytical models; Capacitance; Circuit faults; Circuit noise; Computer aided manufacturing; Coupling circuits; Crosstalk; Laboratories; Mathematics; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
ISSN
1093-0167
Print_ISBN
0-7695-2134-7
Type
conf
DOI
10.1109/VTEST.2004.1299234
Filename
1299234
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