Title :
Architectures for wavelet transforms
Author :
Chakrabarti, Chaitali ; Vishwanath, Mohan ; Owens, Robert M.
Author_Institution :
Dept. of EE, Arizona State Univ., Tempe, AZ, USA
Abstract :
A wide range of architectures for computing 1-D and 2-D DWT, and 1-D and 2-D CWT are presented. These architectures range from systolic arrays and parallel filters to SIMD arrays. The systolic array and the parallel filter architectures require an area that is independent of the length of the input sequence, and support single chip implementation. The SIMD architectures, on the other hand, are optimized for time, and have an area that is proportional to the size of the input
Keywords :
VLSI; parallel architectures; reconfigurable architectures; recursive filters; systolic arrays; transforms; wavelet transforms; 1-D; 2-D; SIMD arrays; VLSI; continuous wavelet transform; discrete wavelet transform; parallel filters; systolic arrays; wavelet transforms; Computer architecture; Continuous wavelet transforms; Discrete wavelet transforms; Filters; Frequency; Numerical analysis; Signal analysis; Signal resolution; Systolic arrays; Wavelet transforms;
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
DOI :
10.1109/VLSISP.1993.404454
