DocumentCode
2993295
Title
A history model for managing the VLSI design process
Author
Chiueh, Tzi-cker ; Katz, Randy
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
358
Lastpage
361
Abstract
A history model is proposed to support the dynamic aspects of VLSI design, i.e., the controlled and disciplined sequencing of CAD tool invocations. This model is based on a task specification language, for encapsulating CAD tool invocations, and a novel activity thread, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. A prototype was built on top of the OCT CAD framework.<>
Keywords
VLSI; circuit CAD; CAD tool; OCT CAD framework; VLSI design process; history model; managing; prototype; sequencing; task specification language; Data structures; Database systems; Design automation; History; Object oriented modeling; Organizing; Process design; Prototypes; Very large scale integration; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129924
Filename
129924
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