DocumentCode :
2993405
Title :
Hierarchical dummy fill for process uniformity
Author :
Chen, Yu ; Kahng, Andrew ; Robins, Garry ; Zelikovsky, Alexander
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
139
Lastpage :
144
Abstract :
To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting “fill” geometries into the layout. Previous approaches for flat layout density control are not scalable due to the necessity of solving very large linear programs, the large data volume of the solution, and the impact of hierarchy-breaking on verification. In this paper, we give the first methods for hierarchical layout density control for process uniformity. Our approach trades off naturally between runtime, solution quality, and output data volume. We also allow generation of compressed GDSII of fill geometries. Our experiments show that this hybrid hierarchical filling approach saves data volume and is scalable, while yielding solution quality that is competitive with existing Monte-Carlo and linear programming based approaches
Keywords :
circuit layout CAD; design for manufacture; integrated circuit layout; integrated circuit manufacture; DFM; IC layout; compressed GDSII; fill geometries insertion; hierarchical dummy fill; hierarchical layout density control; manufacturability improvement; performance predictability; prescribed density criteria; process uniformity; scalable approach; Capacitance; Chemical vapor deposition; Computational geometry; Computer aided manufacturing; Computer science; Copper; Etching; Filling; Process control; Proximity effect;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
Type :
conf
DOI :
10.1109/ASPDAC.2001.913294
Filename :
913294
Link To Document :
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