A 600 MHz half-bit level pipelined accumulator-interleaved multiplier accumulator core

A variety of Digital Signal Processing Algorithms can be realised as a Multiplication and Accumulation Process. Though high throughput multipliers are easy to realise, the throughput of a multiplier accumulator (MAC) is constrained by the rate at which the multiplied products can be accumulated or added together. The authors propose to use a method called accumulator interleaving to break this bottleneck of carry-save accumulation delay. The accumulator interleaved MAC can be pipelined at the level of an XOR gate, thereby achieving a high throughput of 600 MHz. The high speed can be exploited to facilitate folding of the architecture for better hardware utilisation. The multiplier-accumulator unit finds application as a macrocell for realisation of linear recursive and non-recursive DSP algorithms