A methodology for design and evaluation of redundancy allocation algorithms

Author

Shoukourian, S. ; Vardanian, V.A. ; Zorian, Y.

Author_Institution

Virage Logic, Fremont, CA, USA

fYear

2004

fDate

25-29 April 2004

Firstpage

249

Lastpage

255

Abstract

A methodology for design and evaluation of redundancy allocation algorithms based on prime algorithms is proposed for memory devices with spare elements. The methodology can be applied to any memory device with spare elements. It allows the design of simple but effective built-in redundancy allocation (BIRA) algorithms working "on-the-fly" with BIST. The methodology allows also reasonable trade-off between repair coverage and hardware/time complexity during the implementation. A basic toolset for design and evaluation of BIRA algorithms based on the proposed methodology is developed and preliminary results of experiments on the application of the tool for self-test and repair (STAR) type SRAM memories are adduced.

Keywords

SRAM chips; built-in self test; integrated circuit testing; redundancy; BIST; SRAM memory; built in redundancy allocation algorithm; hardware/time complexity; memory devices; self test and repair; Algebra; Algorithm design and analysis; Built-in self-test; Design methodology; Hardware; Logic design; Logic devices; Random access memory; Redundancy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2004. Proceedings. 22nd IEEE

ISSN

1093-0167

Print_ISBN

0-7695-2134-7

Type

conf

DOI

10.1109/VTEST.2004.1299251

Filename

1299251