Title :
Generalized sensitization using fault tuples
Author :
Biswas, Sounil ; Dwarakanath, Kumar N. ; Blanton, R.D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Fault tuples have introduced a fault model independent methodology for digital circuit test analysis. However, the {0, 1, X} algebra currently used with fault tuples allows only one form of path sensitization. The sensitization options for fault tuples is enhanced based on a 5-value algebra. The 5-value algebra enables a more detailed test analysis through the selection of one of three types of sensitization. Simulation experiments performed using the ITC´99 benchmark circuits for transition and path delay faults reveal that faults can be simultaneously analyzed under different types of sensitization criteria with little increase in memory and CPU time.
Keywords :
algebra; digital circuits; fault simulation; logic simulation; logic testing; ITC-99 benchmark circuits; digital circuit test analysis; fault model; fault tuples; five value sensitization algebra; generalized path sensitization; path delay faults; Algebra; Analytical models; Benchmark testing; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Digital circuits; Performance analysis;
Conference_Titel :
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
Print_ISBN :
0-7695-2134-7
DOI :
10.1109/VTEST.2004.1299256