State assignment techniques in multiple-valued logic

Multiple-Valued Logic (MVL) functions are implemented via Boolean multiple-wire arrangements where a careful state assignment methodology is used to ensure efficient implementation regimes. A `power of N´ module is proposed for GF (2³). The method avoids the need to factorize the polynomial and circuits can be realised using a combination of NOT AND and XOR functions. In addition, a novel transform over GF (2²) is proposed which shows promise when compared to the Reed-Muller-Fourier transform, in its capacity to produce zero coefficients. A possible implementation strategy, using Field Programmable Gate Arrays (FPGAs) is briefly discussed