• DocumentCode
    2993860
  • Title

    A new technology mapping for CPLD under the time constraint

  • Author

    Kim, Jae-Jin ; Kim, Hi-Seok ; Lin, Chi-Ho

  • Author_Institution
    Dept. of Electron. Eng., Chongju Univ., South Korea
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    235
  • Lastpage
    238
  • Abstract
    In this paper, we proposed a new technology mapping algorithm for CPLD under the time constraint (TMCPLD-II). In our technology mapping algorithm, we generate the feasible clusters from a given Boolean. The generated feasible clusters create clusters with minimum area under the time constraint. A covered Boolean network is transformed to a Boolean equation. The transformed equations are reconstructed in order to fit to an architecture of selected target CPLD by using collapsing and bin-packing. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the existing algorithms. The experimental results show that our approach is better than any of the existing algorithms in the number of logic blocks
  • Keywords
    bin packing; circuit CAD; integrated circuit design; logic CAD; programmable logic devices; Boolean equation; CPLD; TMCPLD-II algorithm; bin-packing; collapsing; covered Boolean network; feasible clusters generation; logic blocks; technology mapping algorithm; time constraint; Circuit synthesis; Clustering algorithms; Combinational circuits; Computer science; Digital circuits; Educational technology; Equations; Field programmable gate arrays; Logic functions; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-6633-6
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2001.913311
  • Filename
    913311