• DocumentCode
    2993988
  • Title

    A dynamically phase adjusting PLL with a variable delay

  • Author

    Yasuda, Takeo ; Fujita, Hiroaki ; Onodera, Hidetoshi

  • Author_Institution
    Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    275
  • Lastpage
    280
  • Abstract
    Phase locked loops (PLLs) are widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL
  • Keywords
    circuit simulation; delays; digital phase locked loops; controllable delay; digital PLL; dynamically phase adjusting PLL; full loop model simulation; lock-up performance; phase adjust method; variable delay; Circuit simulation; Clocks; Delay effects; Electronic mail; Filters; Hard disks; Informatics; Phase frequency detector; Phase locked loops; Phase measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-6633-6
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2001.913318
  • Filename
    913318