• DocumentCode
    2994021
  • Title

    Computing the error escape probability in count-based compaction schemes

  • Author

    Ivanov, A. ; Zorian, Y.

  • Author_Institution
    Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
  • fYear
    1990
  • fDate
    11-15 Nov. 1990
  • Firstpage
    368
  • Lastpage
    371
  • Abstract
    A unified probabilistic model of count-based compaction is presented that relates the probability of occurrence of the ´counted´ events to a circuit´s fault detection probabilities. This model enables an identical treatment to be made of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, and spectral coefficients. Based on this model, the authors propose a computation technique for determining the error escape associated with these specific, as well as more general, count-based compaction techniques, under various error models.<>
  • Keywords
    circuit layout CAD; fault location; count-based compaction schemes; error escape; error escape probability computing; fault detection; spectral coefficients; unified probabilistic model; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Performance analysis; Performance evaluation; Polynomials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-2055-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1990.129927
  • Filename
    129927