Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

Author

Jie Zeng ; Shurong Dong ; Liou, Juin J. ; Yan Han ; Lei Zhong ; Weihuai Wang

Author_Institution

Dept. of Inf. Sci. & Electron. EngineeringElectrostatic Discharge (ESD) Lab., Zhejiang Univ., Hangzhou, China

Volume

62

Issue

2

fYear

2015

fDate

Feb. 2015

Firstpage

606

Lastpage

614

Abstract

A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR´s I-V characteristics is analyzed via TCAD simulation results as well.

Keywords

electrostatic discharge; integrated circuit design; integrated circuit reliability; thyristors; GGISCR; GGnMOS; area efficient ESD protection device; electrostatic discharge protection; gate grounded nMOS; high holding voltage ESD protection device; imbedded floating P+ region; silicon controlled rectifier; Electrostatic discharges; Impact ionization; P-n junctions; Resistance; Robustness; Thyristors; Area efficiency; double snapback phenomenon; floating p+; gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR); high holding voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2381511

Filename

7015670