Design of fast connected components hardware

The intensive use of the connected components algorithms in image analysis and robot vision calls for a very fast implementation of such algorithms suitable for real-time applications. A hardware design is presented which implements the algorithm due to J.T. Schwartz, M. Sharir, and A. Siegel (1985). A prototype board, which does not use special VLSI chips, had been constructed previously that can compute the connected components in a 512×512 binary image in few video frame times (about 300 ms). A real-time version (video speed) in VLSI is proposed