Bit-level concurrency in real-time geometric feature extractions

Author

Liu, Wentai ; Yeh, Tong-Fei ; Batchelor, William E. ; Cavin, Ralph

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

1988

fDate

5-9 Jun 1988

Firstpage

957

Lastpage

962

Abstract

An efficient mapping from a tree structure into a pipelined array of 2log N states is presented for processing an N×N image. In the proposed mapping structure the identification of the information growing property inherent in feature-extraction algorithms allows bit-level concurrency to be exploited in the architectural design. Accordingly, the design of each staged pipelined processor is simplified

Keywords

computerised pattern recognition; computerised picture processing; parallel architectures; real-time systems; bit-level concurrency; computerised pattern recognition; computerised picture processing; information growing property; mapping structure; parallel architectures; pipelined processor; real-time geometric feature extractions; Binary trees; Computer architecture; Computer vision; Concurrent computing; Feature extraction; Image segmentation; Intelligent robots; Machine vision; Pipeline processing; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Vision and Pattern Recognition, 1988. Proceedings CVPR '88., Computer Society Conference on

Conference_Location

Ann Arbor, MI

ISSN

1063-6919

Print_ISBN

0-8186-0862-5

Type

conf

DOI

10.1109/CVPR.1988.196348

Filename

196348

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2994250