An automated design process for the CHAMP module

Along with problem domains of increasing complexity such as image processing, speech processing, feature identification and feature tracking has come the need for preprocessing of large data sets in real time. Recent advances in Field Programmable Gate Array (FPGA) technologies, both hardware and software, have made reconfigurable preprocessors with custom hardware performance and generic hardware flexibility a reality. A recent example of this is the Configurable Hardware Algorithm Mappable Preprocessor (CHAMP). Initial experience with CHAMP has made clear the need for an automated tools based approach to the problem of algorithm partitioning into multiple FPGAs. The design process for a multiple FPGA module with a goal of >80% utilization and 20 MHz performance required several man weeks of effort and experienced engineers with specific design skills. Dramatically improved synthesis, partitioning, placement and routing tools have made an automated design process targeting a design implemented with high performance FPGAs possible. In this paper the problem of improving and automating the CHAMP algorithm mapping process by utilizing the Firm Macro Library (FML) is discussed. The automated process begins with a VHDL description which is then synthesized into a Xilinx Netlist File (XNF). The XNF file is then partitioned into FPGAs in a two step process. The FML is used to provide highly optimized functional elements to the design process which guarantees the performance and density requirements of the CHAMP