Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modem

Author

Yu, Hyeongseok ; Kim, Byung Wook ; Cho, Yeon Gon ; Cho, Jun Dong ; Kim, Jea Woo ; Lee, Jae Kon ; Park, Hyeon Cheol ; Lee, Ki Won

Author_Institution

Dept. of Electr. & Comput. Eng., Sung Kyun Kwan Univ., Seoul, South Korea

fYear

2001

fDate

2001

Firstpage

404

Lastpage

407

Abstract

In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in a reusable VLSI structure using an EDA tool due to its regular structure. The main idea is to employ a time-multiplexed design scheme grouping the adjacent filter taps with correlated internal dataflow and with data transfer having same processing sequence between blocks. We simulated the proposed design scheme using SYNOPSYS^TM and SPW^TM

Keywords

FIR filters; VLSI; decision feedback equalisers; digital signal processing chips; modems; quadrature amplitude modulation; time division multiplexing; 64/256 QAM modulators; EDA tool; QAM modem; VLSI DFE; adjacent filter taps; area-efficient VLSI architecture; decision feedback equalizer; reusable VLSI architecture; time-multiplexed design scheme; Adaptive filters; Computer architecture; Decision feedback equalizers; Delay; Feedback loop; Finite impulse response filter; Hardware; Modems; Quadrature amplitude modulation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913341

Filename

913341