• DocumentCode
    2994689
  • Title

    Improved alternative wiring scheme applying dominator relationship

  • Author

    Sze, Chin-Ngai ; Wu, Yu-Liang

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    473
  • Lastpage
    478
  • Abstract
    In this paper, we present a competent algorithm to the alternative wiring problem by exploring the relationship between dominators of a target wire. Alternative wiring refers to the process of adding a redundant connection to a circuit such that a target connection will become redundant and can be removed from the circuit without altering the functionality of the circuit. The well-known ATPG-based alternative wiring scheme, redundancy addition and removal for multi-level Boolean optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. The deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires in the circuit. Implication-tree based alternative wiring logic transformation algorithm (IBAW) improves the speed of RAMBO by introducing an implication-tree structure for source node identification. Our approach of investigating the dominator relationship suggests that a large subset of unnecessary redundancy checks can be further avoided in order to improve the efficiency. Experiments were performed on MCNC benchmark circuits and results are compared to those of RAMBO and IBAW. Results show that our proposed algorithm improves IBAW with a 2.3 times speedup. Moreover, our implementation runs 8.8 times faster than RAMBO while solution quality is still maintained
  • Keywords
    Boolean functions; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; multivalued logic circuits; redundancy; trees (mathematics); wiring; MCNC benchmark circuits; alternative wiring problem; dominator relationship; execution time; implication-tree based alternative wiring logic transformation algorithm; multi-level Boolean optimization; redundancy addition; redundancy identification; redundant connection; solution quality; source node identification; Automatic test pattern generation; Circuit optimization; Circuit synthesis; Computer science; Delay; Field programmable gate arrays; Logic; Random access memory; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-6633-6
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2001.913353
  • Filename
    913353