DocumentCode :
2994706
Title :
On-chip power-on reset strategy and I/O power supply detection for VLSI circuits
Author :
Burdia, Danut ; Lazar, Georgian-Alexandru ; Lazar, Luminita-Camelia ; Buzatu, Nicoleta-Roxana
Author_Institution :
Fac. of Electron., Telecommun. & Inf. Technol., Gh. Asachi Tech. Univ. of Iasi, Iasi, Romania
fYear :
2009
fDate :
9-10 July 2009
Firstpage :
1
Lastpage :
4
Abstract :
Many of the complex VLSI systems have separate I/O and core supplies and follow a predefined power up sequence. In this paper, an on-chip power-on reset (POR) strategy and an I/O power supply detection circuit with low steady-state power consumption are proposed. Our technique allows the I/O power supply monitoring, independently from the core power supplies. The I/O power supply detection circuit can detect both ramp up and ramp down of the supply voltage and has a fixed detection threshold. The circuit can operate for any I/O supply voltage level ranging from 1.5 V to 3.3 V. Simulation results show a maximum steady state power consumption of 23 muW. Due to this fact the proposed POR circuit is suitable for low power applications and embedding in portable device systems.
Keywords :
VLSI; power supply circuits; I/O power supply detection; I/O power supply monitoring; VLSI circuit; on-chip power-on reset strategy; power 23 muW; voltage 1.5 V to 3.3 V; Circuits; Communication standards; Detectors; Energy consumption; Low voltage; Monitoring; Power supplies; Signal generators; Steady-state; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on
Conference_Location :
Iasi
Print_ISBN :
978-1-4244-3785-6
Electronic_ISBN :
978-1-4244-3786-3
Type :
conf
DOI :
10.1109/ISSCS.2009.5206160
Filename :
5206160
Link To Document :
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