Optimization of Speed and Power in a 16-Bit Carry Skip Adder in 70nm Technology

In this article, speed and power dissipation of a 16-bit carry skip adder will be optimized using different optimization methods. This adder is implemented in 70nm technology. First the worst carry propagation time will be reduced by changing logic style and using Genetic Algorithm to optimize the skip network of the circuit. And then the power dissipation of the circuit will be optimized by applying MTCMOS technology and Genetic Algorithm optimization on feature size of the transistors. With these methods we reached 7% improvement in circuit performance and 44% reduction in power consumption of the circuit.