A computer aided engineering system for memory BIST

Author

Su, Chauchin ; Hsiao, Shih-Ching ; Zhau, Hau-Zen ; Lee, Chung-Len

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

fYear

2001

fDate

2001

Firstpage

492

Lastpage

495

Abstract

An integrated memory test system is presented. It includes a reconfigurable memory test module, a test algorithm editor, a memory fault simulator, and a test code generator. For a given memory organization, fault list, and test algorithm, the system automatically reports the fault coverage, generates control assembly codes, and produces circuit net list for test pattern generation. The system has been implemented in 9000 lines of C++ program based on the Microsoft Windows graphic user interface. It has been verified on different test algorithms and memory chips

Keywords

automatic test pattern generation; built-in self test; computer aided engineering; fault simulation; integrated circuit testing; integrated memory circuits; logic testing; C++ program; circuit net list; computer aided engineering system; control assembly codes; fault coverage; fault list; graphic user interface; memory BIST; memory chips; memory fault simulator; memory organization; reconfigurable memory test module; test algorithm; test algorithm editor; test algorithms; test code generator; test pattern generation; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer aided engineering; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913356

Filename

913356