• DocumentCode
    2994950
  • Title

    Coarse grain reconfigurable architectures

  • Author

    Hartenstein, Reiner

  • Author_Institution
    Dept. of Comput. Sci., Kaiserslautern Univ., Germany
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    564
  • Lastpage
    569
  • Abstract
    The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing
  • Keywords
    application specific integrated circuits; logic CAD; program compilers; reconfigurable architectures; coarse grain reconfigurable architectures; compilation techniques; reconfigurable computing; Computer architecture; Fabrics; Field programmable gate arrays; Hardware; Neural networks; Reconfigurable architectures; Research and development; Routing; Systolic arrays; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-6633-6
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2001.913368
  • Filename
    913368
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2994950