DocumentCode :
2994982
Title :
Efficient global fanout optimization algorithms
Author :
Murgai, Rajeev
Author_Institution :
Fujitsu Labs. of America Inc., CA, USA
fYear :
2001
fDate :
2001
Firstpage :
571
Lastpage :
576
Abstract :
Fanout optimization is a fundamental problem in timing optimization. Most of the research has focussed on the fanout optimization problem for a single net (or the local fanout optimization problem-LFO). The real goal, however, is to optimize the delay through the entire circuit by fanout optimization incurring minimum area penalty and without violating the pin loading constraints. This is known as the global fanout optimization (GFO) problem. In this paper, we show that the techniques proposed so far in the literature are either impractical or ineffective for large designs. We propose simple yet efficient and effective schemes for GFO and show that they outperform the “nearly-optimum” reverse topological (RT) algorithm on large industrial designs. One of these schemes yields only 0.3% worse circuit delay on average, but incurs only 18.5% of the area penalty as compared to the RT algorithm and is about 3 times faster. A popularly used mincut-based strategy was not found to be effective
Keywords :
circuit optimisation; delays; network topology; timing; area penalty; circuit design; delay model; global fanout optimization algorithm; integer linear programming algorithm; mincut algorithm; pin loading; reverse topological algorithm; timing; Algorithm design and analysis; Capacitance; Circuits; Constraint optimization; Delay effects; Design optimization; Laboratories; Logic; Pins; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
Type :
conf
DOI :
10.1109/ASPDAC.2001.913369
Filename :
913369
Link To Document :
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