Title :
On speeding up extended finite state machines using catalyst circuitry
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block-which includes a piece of combinational logic and several other registers-to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit´s functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial application-a BIST circuit for SRAMs. The synthesis result indicates a 47% clock cycle time reduction
Keywords :
SRAM chips; built-in self test; combinational circuits; finite state machines; logic CAD; minimisation of switching nets; state assignment; timing; BIST circuit; CMOS standard cell; RTL code; catalyst circuitry; clock cycle time reduction; combinational logic; complex finite state machine; data operators; extended finite state machines; functionally redundant block; high-speed architecture; prediction logic; random logic; static random access memories; timing critical path; timing optimization technique; Automata; Built-in self-test; Clocks; Combinational circuits; Counting circuits; Logic design; Pipeline processing; Registers; SRAM chips; Timing;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913371
